Method and circuit for reducing noise in a capacitive sensing device

ABSTRACT

A capacitive sensing circuit is provided. The capacitive sensing circuit includes a first capacitor and a charge-to-voltage converter circuit coupled to the first capacitor. The charge-to-voltage converter circuit includes a first current source that provides a first current to the first capacitor to charge the first capacitor and generate a time-varying voltage. The capacitive sensing circuit also includes a voltage-to-charge converter circuit coupled to the charge-to-voltage converter circuit, wherein the voltage-to-charge converter circuit samples the time-varying voltage and converts the time-varying voltage into a sampled charge at a predetermined sampling frequency. The capacitive sensing circuit further includes an integrator circuit coupled to the voltage-to-charge circuit, wherein the integrator circuit receives the sampled charge and integrates the sampled charge.

BACKGROUND

1. Technical Field

The present disclosure is related to capacitive sensing devices and, inparticular, a method and circuit for reducing noise in a capacitivesensing device.

2. Discussion of Related Art

Capacitive sensing devices are found in many of today's electronics. Inparticular, capacitive sensing devices are often found in handhelddevices for enabling the touch screens of these devices. In thesehandheld devices, the capacitive sensing device detects the position onthe screen of an operator's finger or other pointing device such as astylus. The detected position is then interpreted by a processor toexecute a program, move a cursor, or select an icon displayed on thetouch screen. The capacitive sensing devices typically include acapacitive sensor, such as the sensor shown in FIGS. 1A, 1B, and 2.

FIG. 1A is a diagram illustrating a conventional two-terminal capacitivesensor 100. As shown in FIG. 1A, capacitive sensor includes a sensecapacitor 102, which produces a voltage Vs₁ and Vs₂ at each plate ofcapacitor 102 proportional to a charge stored on capacitor 102. A firstswitch 104 is coupled in parallel to sense capacitor 102, and a secondswitch 106 is coupled to a top plate of sense capacitor 102 and a thirdswitch 108 is coupled to a bottom plate of sense capacitor 102. Whensecond switch 106 is closed, integrator circuit 110 is coupled to sensecapacitor 102, and when third switch 108 is closed, sense capacitor 102is coupled to ground. As shown in FIG. 1A, integrator circuit 110includes an integration capacitor 112 coupled to an amplifier 114 in anegative feedback loop. A reference voltage V_(ref) is input into thepositive terminal of amplifier 114. In operation, capacitive sensor 100uses a series of charge and discharge pulses to transfer a quantum ofcharge into integration capacitor 112. After a predetermined interval oftime, the quantum of charge stored in integration capacitor 112 ismeasured. The measurement of the charge stored in integration capacitor112 is proportional to the charge stored in sense capacitor 102, and canbe used to estimate the value of the charge stored in sense capacitor102. Generally, the amount of charge Q stored on a capacitor isproportional to the voltage V across the terminals of the capacitor,such that Q=CV, C being the capacitance of the capacitor in farads.

In operation, capacitive sensor 100 is charged and discharged using afixed clock frequency having a period of T_(s). FIG. 1B is a timingdiagram illustrating the charge and discharge timing of the sensorillustrated in FIG. 1A. As shown in FIG. 1B, during every period T_(s),P₁ goes to a high state then a low state, and then P₂ goes to a highstate and then a low state. When P₁ is at a high state, second switch106 and third switch 108 are closed, and sense capacitor 102 is charged.When P₂ is at a high state, first switch 104 is closed, and sensecapacitor 102 is discharged. This charge and discharge cycle allows fora charge to be built up on sense capacitor 102, and then dischargedwhile a charge proportional to the charge stored on sense capacitor 102to be sampled by integrator circuit 110 and measured. While thecapacitive sensor 100 illustrated in FIGS. 1A and 1B can be used whenboth plates of sense capacitor 102 are forced to fixed voltages such asVs₁ and Vs₂, many capacitive sensors have a plate that is coupled toground.

FIG. 2 is a diagram illustrating a single terminal capacitive sensor 200according to the prior art. As shown in FIG. 2, capacitive sensor 200includes a sense capacitor 202 which has a top plate which is coupled tointegrator circuit 204 via first switch 206, and bottom plate which iscoupled to ground. Second switch 208, when closed and when first switch206 is open, provides a path to ground for sense capacitor 202, allowingfor the charge and discharge of sense capacitor 202 via the opening andclosing of switches 206 and 208, similar to FIGS. 1A and 1B. Similar tointegrator circuit 110, integrator circuit 204 includes an integrationcapacitor 210 coupled in a negative feedback loop with amplifier 212.However, as shown in FIG. 2, sense capacitor 202 having its back platecoupled to ground results in noise V_(N) which can affect themeasurements by the integrator circuit 204, resulting in an inaccuratedetermination of the charge stored in sense capacitor 202.

Prior art attempts to minimize the noise appearing in the measured valuehave involved making successive measurements and integrating the chargeon integration capacitor 210. Although this technique may improve thesignal-to-noise ratio of the measurement with respect to certainfrequencies of noise, it creates additional problems. For example,because the measurement involves repeated sampling of the charge,aliasing of the noise arises at the charge-discharge frequency, 1/T_(s).This aliasing is indistinguishable from the capacitance of sensecapacitor 202, making it very difficult to process out of the measuredsignal. Moreover, this aliasing becomes even more problematic inenvironments where there are many electrically driven sources operatingtogether, each of which have periodic repetition frequency signals.

However, because the quantum of charge is not dependent on theduty-cycle of the charge-discharge pulse but only the charge-dischargefrequency (F_(s)=1/T_(s)), other prior art attempts to minimize thenoise appearing in the measured value have involved periodicallychanging the clock frequency, known as dithering the clock frequency orspread-spectrum clocking. Dithering the clock frequency orspread-spectrum clocking typically uses a clock having a frequencyhigher than charge-discharge frequency and passing the clock through adual-modulus (N/N+1) frequency divider. The clock frequency randomlychanges between F_(s) and (1+1/N)·F_(s) when the modulus is adjusted,which serves to mitigate some of the noise aliasing from multiples ofthe charge-discharge frequency F_(s). However, this solution is alsovery imperfect because during measurement intervals when thecharge-discharge frequency F_(s) is equal to the clock frequency, thereis perfect aliasing of the noise at multiples of the charge-dischargefrequency F_(s) to direct current DC which cannot be removed from themeasurement. In order for this solution to substantially reduce noisesensitivity, a multi-modulus frequency divider needs to be used, whichmay increase the size of the sensing device and increase powerdissipation due to a higher fundamental clock frequency required.

Therefore, there is a need to develop a capacitive sensing device thathas improved noise characteristics using noise reduction techniqueswhich do not alias the noise created by coupling a bottom plate of asense capacitor to ground.

SUMMARY

Consistent with embodiments of the present disclosure, a capacitivesensing circuit is provided. The capacitive sensing circuit includes afirst capacitor and a charge-to-voltage converter circuit coupled to thefirst capacitor. The charge-to-voltage converter circuit includes afirst current source that provides a first current to the firstcapacitor to charge the first capacitor and generate a time-varyingvoltage. The capacitive sensing circuit also includes avoltage-to-charge converter circuit coupled to the charge-to-voltageconverter circuit, wherein the voltage-to-charge converter circuitsamples the time-varying voltage and converts the time-varying voltageinto a sampled charge at a predetermined sampling frequency. Thecapacitive sensing circuit further includes an integrator circuitcoupled to the voltage-to-charge circuit, wherein the integrator circuitreceives the sampled charge and integrates the sampled charge.

Consistent with some embodiments, there is also provided a method ofgenerating a signal proportional to a charge of a capacitor, thegenerated signal having reduced noise. The method includes generating atime-varying voltage across a first capacitor by supplying a firstcurrent produced by a first current source to the capacitor, wherein avoltage build up on the first capacitor is periodically reset, samplingthe time-varying voltage, generating a proportional charge that isproportional to a charge stored on the first capacitor based on thesampled time varying voltage, and accumulating the proportional chargeon a second capacitor.

These and other embodiments will be described in further detail belowwith respect to the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram illustrating a two-terminal capacitive sensoraccording to the prior art.

FIG. 1B is a timing diagram illustrating the charge and discharge timingof the sensor illustrated in FIG. 1A.

FIG. 2 is a diagram illustrating a single terminal capacitive sensoraccording to the prior art.

FIG. 3 is a diagram illustrating a capacitive sensor consistent withsome embodiments.

FIG. 4 is a diagram illustrating a charge-to-voltage converter circuitconsistent with some embodiments.

FIG. 5A is a diagram illustrating a voltage-to-charge converter circuitconsistent with some embodiments.

FIG. 5B is a timing diagram illustrating the timing of the circuitillustrated in FIG. 5A.

FIG. 6 is a diagram illustrating a voltage-to-charge converter circuitconsistent with some embodiments.

FIG. 7 is a timing diagram illustrating the timing of the circuitillustrated in FIG. 6.

FIG. 8 is a diagram illustrating a charge-to-voltage circuit consistentwith some embodiments.

FIGS. 9A and 9B are diagrams illustrating a voltage-to-charge convertercircuit consistent with some embodiments.

FIG. 10 is a timing diagram illustrating the timing of both processingstages of the circuits illustrated in FIGS. 9A and 9B.

FIG. 11 is a flowchart illustrating a method for generating a signalproportional to a charge of a capacitor having reduced noise consistentwith some embodiments.

In the drawings, elements having the same designation have the same orsimilar functions.

DETAILED DESCRIPTION

In the following description specific details are set forth describingcertain embodiments. It will be apparent, however, to one skilled in theart that the disclosed embodiments may be practiced without some or allof these specific details. The specific embodiments presented are meantto be illustrative, but not limiting. One skilled in the art may realizeother material that, although not specifically described herein, iswithin the scope and spirit of this disclosure.

Consistent with some embodiments, a capacitive sensor as describedherein includes a two-stage architecture. The first stage may be acharge-to-voltage conversion circuit that includes an exciting sourcefor charging a sense capacitor and generating a time-varying voltage.The second stage may be a voltage-to-charge conversion circuit thatconverts the generated time-varying voltage to a charge that isproportional to a charge on the sense capacitor. The sampled charge isthen input into an integrator that provides a measurement of the chargestored on the sense capacitor from the proportional charge generated inthe voltage-to-charge generating circuit.

Consistent with some embodiments, a fixed current source is used tocharge the sense capacitor, and the voltage build up on the sensecapacitor is periodically reset to zero by using at least one of a resetpulse or by changing the polarity of the fixed current source. In suchembodiments, the voltage on the sense capacitor V_(c) is given by thefollowing equation:

${V_{c} = {{\frac{1}{C_{s}}{\int_{T_{0}}^{T_{1}}{I_{Ref}{t}}}} + {\int_{T_{0}}^{T_{1}}{{V_{n}(t)}{t}}}}},$

where C_(s) is the capacitance of the sense capacitor, V_(n) is thenoise voltage transient at the back plate of the sense capacitor,I_(Ref) is the value of the fixed current source, T₀ is the time atwhich the periodic reset of the sense capacitor is released, and T₁ isthe time at which the voltage sample is taken.

The above equation is useful in facilitating the rejection of noise at asampling frequency F_(s) and multiples of the sampling frequency, i.e.,k·F_(s). For example, for all noise signals, if the time at which thevoltage sample is taken T₁ can coincide with the sampling F_(s), allnoise frequencies which are at multiples of the sampling frequency F_(s)will result in zero aliasing. This is because multiples of the samplingfrequency k·F_(s) can be represented as A_(n) sin(k2πF_(s)), where A_(n)represents the amplitude of the external (periodic) noise source, andthe integral of A_(n) sin(k2πF_(s)) over the period from any time atwhich the periodic reset of the sense capacitor is released (n+1)T_(s)and any time at which the voltage sample is taken nT_(s) is equal tozero irrespective of the value of A_(n).

Based on this information, FIG. 3 is a diagram illustrating a capacitivesensor 300 consistent with some embodiments. As shown in FIG. 3,capacitive sensor 300 includes a sense capacitor 302 having a back platewhich is coupled to ground. The front plate of sense capacitor 302 iscoupled to two circuits which may implement a two stage process forcharging and discharging sense capacitor 302 and then sampling a chargefrom sense capacitor 302. In particular, sense capacitor 302 is firstcoupled to a charge-to-voltage converter circuit 304. Charge-to-voltageconverter circuit 304 includes a current source for charging sensecapacitor 302 and generating a time-varying voltage V_(s).Charge-to-voltage converter circuit 304 also includes circuitry forperiodically discharging a voltage build up on sense capacitor 302.

Charge-to-voltage converter circuit 304 is coupled to avoltage-to-charge converter circuit 306 that receives the time-varyingvoltage V_(s) generated by charge-to-voltage converter circuit 304.Voltage-to-charge converter circuit 306 generates a sampled charge fromthe time-varying voltage V_(s) that is proportional to the charge onsense capacitor 302 by sampling the time-varying voltage V_(s) andgenerating a charge proportional to the sampled voltage or a derivativeof the sampled voltage depending on the clock phase. The chargegenerated by voltage-to-charge converter circuit 306 is accumulated inan integrator circuit 308 for providing a measurement of the chargestored on sense capacitor 302. Similar to prior art integrator circuits,integrator circuit 308 includes an integration capacitor 310 coupled toan amplifier 312 in a negative feedback loop, wherein the measurement ofthe charge stored in integration capacitor 310 is proportional to thecharge stored in sense capacitor 302, and can be used to estimate thevalue of the charge stored in sense capacitor 302.

Similar to the prior art device shown in FIG. 2, because capacitor 302has a back plate that is coupled to ground, noise is introduced, shownas V_(N). However, unlike the prior art device shown in FIG. 2, insteadof using fixed voltage references and switches that periodically connectthese references to charge or discharge the sense capacitor of thecapacitive sensor, capacitive sensor 300 generates a charge proportionalto sense capacitor 302 without incurring aliasing noise from the groundof sense capacitor 302.

FIG. 4 is a diagram illustrating a charge-to-voltage converter circuit304 consistent with some embodiments. As shown in FIG. 4,charge-to-voltage converter circuit 304 is coupled to sense capacitor302 and provides circuitry for charging and discharging sense capacitor302 to generate time-varying voltage V_(s) on sense capacitor 302.Charge-to-voltage converter circuit 304 includes a current source 402that is coupled to sense capacitor 302 and provides a current I_(Ref)for charging sense capacitor 302. Current source 402 is further coupledto a unity gain buffer 404, which outputs time-varying voltage V_(s) tovoltage-to-charge converter circuit 306. Sense capacitor 302 and currentsource 402 are further coupled to a switch 406 which, when closed,provides a path to ground and allows for the discharge of voltage builtup on sense capacitor 302. Switch 406 is periodically closed by theapplication of a reset pulse P_(rst). Depending on the frequency of thereset pulse relative to the sampling frequency, voltage-to-chargeconverter circuit 306 may have different implementations.

FIG. 5A is a diagram illustrating a voltage-to-charge converter circuit306 consistent with some embodiments. As shown in FIG. 5A,voltage-to-charge converter circuit 306 includes a first switch 502coupled between a capacitor 504 and charge-to-voltage converter circuit304. Voltage-to-charge converter circuit 306 further includes a secondswitch 506 coupled between first switch 502 and capacitor 504, a thirdswitch 508 coupled between capacitor 504 and integration circuit 308,and a fourth switch 510 coupled between capacitor 504 and third switch508. Consistent with some embodiments, voltage-to-charge convertercircuit 306 as shown in FIG. 5A may be used when the frequency of resetpulse P_(rst) is the same as sampling frequency F_(s). Moreover, themagnitude of noise rejections at multiples of the sampling frequencyk·F_(s) is inversely proportional to the duration of reset pulse P_(rst)relative to the sampling period T_(s).

As shown in FIG. 5A, voltage-to-charge converter circuit is primarily intwo states (a) and (b). In state (a), the time-varying voltage issampled and applied across capacitor 504, accumulating charge oncapacitor 504. In state (b), first switch 502 and fourth switch 510 areopened and second switch 506 and third switch 508 are closed, allowing avoltage V_(int) generated by the charge accumulated on capacitor 504 tobe passed to integration circuit 308. Thus, states (a) and (b) aretoggled by the opening and closing of switches 502, 506, 508, and 510.In particular, when switches 502 and 510 are closed and switches 506 and508 are toggled open, voltage-to-charge converter circuit 306 is instate (a). When switches 502 and 510 are open and switches 506 and 508are closed, voltage-to-charge converter circuit 306 is in state (b).Consistent with some embodiments, the toggling of switches 502 and 510is controlled by a first pulse signal P₁, and the toggling of switches506 and 508 is controlled by a second pulse signal P₂.

FIG. 5B is a timing diagram illustrating the timing of voltage-to-chargeconverter circuit 306. As shown in FIG. 5B, a clock signal Clk rises andfalls during each sample period T_(s). Periodically, first pulse signalP₁ goes to a high state, which toggles switches 502 and 510 to close. Atthis time, time-varying voltage V_(s) is being sampled and accumulatedon capacitor 504. Consistent with some embodiments, as soon as firstpulse signal P₁ returns to a low state, reset pulse P_(rst) goes to ahigh state, which toggles switch 406 in charge-to-voltage convertercircuit 304, and allows the voltage build up on sense capacitor 302 tobe discharged. In response to the falling edge of reset pulse P_(rst),second pulse signal P₂ transitions to a high state, toggling switches506 and 508 to close such that voltage V_(int) generated by the chargeaccumulated on capacitor 504 can be passed to integration circuit 308.

FIG. 6 is a diagram illustrating a voltage-to-charge converter circuit306 consistent with some embodiments. Voltage-to-charge convertercircuit 306 shown in FIG. 6 is similar to voltage-to-charge convertercircuit 306 shown in FIG. 5A, and can be utilized, for example, when theperiod T_(rst) of the reset pulse P_(rst) is equal to an integermultiple of the sampling period T_(s), i.e., when T_(rst)=n·T_(s).Moreover, voltage-to-charge converter circuit 306 may provide betternoise rejection of noise aliases regardless of the duration of resetpulse P_(rst) relative to sampling period T_(s). Furthermore, when theperiod of the reset pulse T_(rst) is equal to multiples of the samplingperiod T_(s), (n−1) periods of integration include the complete samplingperiod T_(s) and the last period of integration may be used to partiallyintegrate and partially reset the sense capacitor.

As shown in FIG. 6, voltage-to-charge converter circuit 306 includes afirst switch 602 coupled between charge-to-voltage converter circuit 304and capacitor 604. A second switch 606 is coupled between capacitor 604and integration circuit 308. A third switch 608 is coupled between afirst voltage source V₁ and first capacitor 604, and a fourth switch 610is coupled between a second voltage source V₂ and capacitor 604. A fifthswitch 612 between capacitor 604 and second switch 606. A sixth switch614 is coupled between charge-to-voltage converter circuit 304 and asecond capacitor 616, and a seventh switch 618 is coupled between secondcapacitor 616 and integration circuit 308.

As shown in FIG. 6, voltage-to-charge circuit may be in one of fourstates depending on the opening and closing of the switches. State (a)is a first sampling stage, wherein first switch 602, fifth switch 612,and sixth switch 614 are closed, and second 606, third 608, fourth 610,and seventh 618 switches are open. In state (a), time-varying voltageV_(s) is sampled from charge-to-voltage circuit 304 and accumulated onfirst capacitor 604 and second capacitor 616. In state (b), switches602, 612, and 614 are opened, while switch 606 is closed, allowing for avoltage V_(int) generated by the charge accumulated on capacitor 604 tobe passed to integration circuit 308. However, in state (b), switch 608is also closed, which applies a voltage source dependent on firstvoltage source V₁ and the time-varying voltage V_(s) accumulated onsecond capacitor 616 to capacitor 604. This voltage source changes thevoltage V_(int) generated by the charge accumulated on capacitor 604 bya predetermined amount. In state (c), switches 602 and 612 are closedand switches 606 and 608 are opened. In state (c), time-varying voltageV_(s) is again sampled from charge-to-voltage circuit 304 andaccumulated on first capacitor 604. However, from state (b), capacitor604 also included a charge dependent on both the charge sampled in state(a) and first voltage source V₁. Thus, the charge accumulated oncapacitor 604 in state (c) are not only based on the time-varyingvoltage V_(s) sampled in state (c), but also the time-varying voltageV_(s) sampled in state (a). Then, in state (d), switches 602 and 612 areopened and switches 606, 610 and 616 are closed. Thus, a second voltagesource V₂ is applied to first capacitor 604 and the integration voltageV_(int) is applied to second capacitor 618. These voltage sources alsochange the voltage V_(int) generated by the charge accumulated oncapacitor 604 by a predetermined amount in subsequent sampling phases.

Consistent with some embodiments, the toggling of switches 602, 612, and614 may be controlled by a first pulse signal P₁. Similarly, switch 608may be controlled by a second pulse signal P₂, switches 610 and 618 maybe controlled by a third pulse signal P₃, and switch 606 may either becontrolled by a fourth pulse signal, or it may be controlled by eitherthe second pulse signal P₂ or the third pulse signal P₃ such that switch606 is toggled closed when either of second pulse signal P₂ and/or thirdpulse signal P₃ are in a high state.

FIG. 7 shows a timing diagram illustrating the timing ofvoltage-to-charge circuit 306 illustrated in FIG. 6. As shown in FIG. 7,a clock signal Clk transitions from a high state to a low state twiceover a single sampling period T_(s). First pulse signal P₁ periodicallytransitions from a high state to a low state, toggling first switch 602,fifth switch 612, and sixth switch 614. When first pulse signal P₁transitions from a high state to a low state, either second pulse signalP₂ transitions to a high state, toggling switch 608 and switch 606 to beclosed, or reset pulse P_(rst) transitions to a high state, whichtoggles switch 406 in charge-to-voltage converter circuit 304, andallows the voltage build up on sense capacitor 302 to be discharged.When reset pulse P_(rst) transitions to a low state, third pulse signalP₃ transitions to a high state, toggling switches 610, 606, and 618 tobe closed. Consistent with some embodiments, zero noise is sampledduring the period of second pulse signal P₂ because the integrationperiod coincides with the noise period. Any noise sampled during theperiod of third pulse signal P₃ will only occur at ½·F_(s). Thus, thisnoise can be easily removed using a digital signal processorspecifically programmed to reduce the noise at ½·F_(s). Any noisealiasing caused by the beat frequencies of the reset pulse frequencyF_(rst) and sampling frequency F_(s) can be handled throughdiscrete-time processing of charge samples. Consistent with theembodiments shown in FIGS. 6 and 7, a discrete-time differentiator canbe used to reject the noise aliasing caused by beat frequencies F_(rst)and F_(s) as the sampled voltage in states (c) and (d) are dependent, inpart, on the sampled voltage in state (a).

FIG. 8 is a diagram illustrating a charge-to-voltage converter circuit304 consistent with some embodiments. As shown in FIG. 8,charge-to-voltage converter circuit 304 is coupled to sense capacitor302 and provides circuitry for charging and discharging sense capacitor302 to generate time-varying voltage V_(s) on sense capacitor 302.Charge-to-voltage converter circuit 304 includes a first current source802 that is coupled to sense capacitor 302 and provides a currentI_(Ref) for charging sense capacitor 302. Charge-to-voltage convertercircuit 304 also includes a second current source 804 that is coupled tosense capacitor 302 and provides a current −I_(Ref) to sense capacitor302 for discharging sense capacitor 302. Charge-to-voltage convertercircuit 304 as shown in FIG. 8 may require using at lease two fullsample periods 2·T_(s) for charging sense capacitor 302 and thefollowing two full sample periods to discharge sense capacitor 302.

Referring to FIG. 8, current sources 802 and 804 are respectivelycoupled to sense capacitor 302 via switches 806 and 808. Consistent withsome embodiments, switch 806 is toggled via a first charge pulse signalP_(ch1) and switch 808 is toggled via a second charge pulse signalP_(ch2) which transitions to a high state when first charge pulse signalP_(ch1) transitions to a low state. Current sources 802 and 804 arefurther coupled to a unity gain buffer 810, which outputs time-varyingvoltage V_(s) to voltage-to-charge converter circuit 306.

FIGS. 9A and 9B are diagrams illustrating the processing stages of avoltage-to-charge converter circuit 306 consistent with someembodiments. In particular, FIG. 9A illustrates a first processing stagethat is used to remove aliases at integer multiples of the samplingfrequency F_(s), and FIG. 9B illustrates a second processing stage thatis used to remove aliases of noises at half the sampling frequency 0.5F_(S). Consistent with the embodiments shown in FIGS. 9A and 9B,voltage-to-charge converter circuit 306 generates a sampled charge to beintegrated which is proportional to an absolute value of the sampledvoltage with respect to a reference voltage V_(R), and the separateprocessing stages shown in FIGS. 9A and 9B operate in parallel.

As shown in FIG. 9A voltage-to-charge converter circuit 306 includes afirst switch 902 coupled between charge-to-voltage converter circuit 304and first capacitor 904. A second switch 906 is coupled betweencapacitor 904 and integration circuit 308. A third switch 908 is coupledbetween a reference voltage source V_(R) and first switch 902, and afourth switch 910 is coupled between reference voltage source V_(R) andsecond switch 906. Voltage-to-charge converter circuit 306 also includesa second capacitor 912 coupled between reference voltage source and afifth switch 914 and a sixth switch 916.

As shown in FIG. 9A, voltage-to-charge circuit 306 may be in one of twostates depending on the opening and closing of the switches. State (a)is a sampling state, wherein first switch 902, fourth switch 910 andfifth switch 914 are closed, and second 906, third 908, and sixth 916switches are open. In state (a), time-varying voltage V_(s) is sampledfrom charge-to-voltage circuit 304 and accumulated on first capacitor904 and second capacitor 912. State (b) is an integration state, whereinswitches 902, 910, and 914 are opened and switches 906, 906, and 916 areclosed, such that a voltage V_(int) generated by the charge accumulatedon first capacitor 904 can be passed to integration circuit 308. Instate (b), a charge dependent on both reference voltage V_(R) andtime-varying voltage V_(s) sampled in state (a) is accumulated on firstcapacitor 904. Consistent with some embodiments, the toggling ofswitches 902, 910 and 914 may be controlled by a first pulse signal P₁and a third pulse signal P₃, and switches 906, 908, and 916 may becontrolled by a second pulse signal P₂ and a fourth pulse signal P₄ asdiscussed below with respect to FIG. 10. Voltage-to-charge convertercircuit 306 as shown in FIG. 9A distinguishes the signal component andaliases of noise at multiples of the sampling frequency F_(s) byconverting the signal component to a direct current (DC) charge, andconverting the aliases of noise to a sinusoidal charge which is removedduring the integration state.

FIG. 9B illustrates a second processing stage that is used to removealiases of noises at half the sampling frequency 0.5 F_(S). As shown inFIG. 9B, the second processing stage of voltage-to-charge convertercircuit 306 includes a first switch 902 coupled betweencharge-to-voltage converter circuit 304 and first capacitor 904. Asecond switch 906 is coupled between capacitor 904 and integrationcircuit 308. A third switch 908 is coupled between a reference voltagesource V_(R) and first switch 902, and a fourth switch 910 is coupledbetween reference voltage source V_(R) and second switch 906.Voltage-to-charge converter circuit 306 also includes a second capacitor912 coupled between reference voltage source V_(R) and a fifth switch914 and a sixth switch 916.

As shown in FIG. 9B, voltage-to-charge circuit 306 may be in one of twostates depending on the opening and closing of the switches. State (a)is a sampling state, wherein first switch 902, fourth switch 910 andfifth switch 914 are closed, and second 906, third 908, and sixth 916switches are open. In state (a), time-varying voltage V_(s) is sampledfrom charge-to-voltage circuit 304 and accumulated on first capacitor904 and second capacitor 912. State (b) is an integration state, whereinswitches 902, 910, and 914 are opened and switches 906, 906, and 916 areclosed, such that a voltage V_(int) generated by the charge accumulatedon first capacitor 904 can be passed to integration circuit 308. Instate (b), a charge dependent on both reference voltage V_(R) andtime-varying voltage V_(s) sampled in state (a) is accumulated on firstcapacitor 904. Similar to FIG. 9A, the toggling of switches 902, 910,and 914 may be controlled by first pulse signal P₁ and third pulsesignal P₃, and switches 906, 908, and 916 may be controlled by secondpulse signal P₂ and fourth pulse signal P₄ as discussed below withrespect to FIG. 10. The second processing stage of voltage-to-convertercircuit 306 as shown in FIG. 9 prevents aliases of noise at half of thesampling frequency F_(s) by subtracting the charges of successivesamples in phases A and B, using a differentiator, and then convertingthe noise to a frequency which can be distinguished from the signal. Thenoise can then be subtracted from the signal, thus preventing noise athalf of the sampling frequency. Similar to the embodiments shown inFIGS. 7 and 8, any noise aliasing caused by the beat frequencies of thecharge pulse frequency F_(ch) and sampling frequency F_(s) can behandled through discrete-time processing of charge samples.

FIG. 10 shows a timing diagram illustrating the timing of bothprocessing stages of voltage-to-charge circuit 306 illustrated in FIGS.9A and 9B. As shown in FIG. 10, a clock signal Clk transitions from ahigh state to a low state twice over a single sampling period T_(s) andthe period of a charge pulse signal P_(ch) being equal to nT_(s) (withn=2 in an embodiment shown in FIG. 10). First pulse signal P₁, secondpulse signal P₂, third pulse signal P₃, and fourth pulse signal P₄ eachhave a first phase A and a second phase B, phase A representing a timewhen a voltage at first capacitor 904 is greater than reference voltageV_(R) and phase B representing a time when a voltage at first capacitor904 is less than reference voltage V_(R). In addition, first pulsesignal P₁ and second pulse signal P₂ represents a time when a derivativeof the voltage at first capacitor 904 is negative, and third pulsesignal P₃ and fourth pulse signal P₄ represent a time when a derivativeof the voltage at first capacitor 904 is positive.

Consistent with the first processing stage shown in FIG. 9A, phase A offirst pulse signal P₁ and third pulse signal P₃ toggles fifth switch914, and phase B of first pulse signal P₁ and third pulse signal P₃toggles first switch 902 and fourth switch 910. Phase A of second pulsesignal P₂ and fourth pulse signal P₄ toggles sixth switch 916, and phaseB of second pulse signal P₂ and fourth pulse signal P₄ toggles secondswitch 906 and third switch 908.

With respect to the second processing stage shown in FIG. 9B, bothphases A and B of third pulse signal P₃ toggles first switch 902 andfourth switch 910. Both phase A of second pulse signal P₂ and phase B offourth pulse signal P₄ toggles second switch 906, third switch 908, andsixth switch 916. Both phase A and phase B of first pulse signal P₁toggles fifth switch 914.

As shown in FIGS. 8, 9A, 9B, and 10, two full sample periods 2T_(s) areused for charging sense capacitor 302, and the following two full sampleperiods are used to discharge sense capacitor 302. This results in aproportional charge to be integrated which is proportional to anabsolute value of the sampled voltage with respect to reference voltageV_(R). Since the integration period with respect to noise is the same asthe sample period T_(s), but the current source switches polarity onceduring the integration cycle, a noise charge having equal but oppositepolarity is injected into the system every other cycle. The firstprocessing stage of voltage-to-charge converter circuit 306 as shown inFIG. 9A distinguishes the signal component and aliases of noise atmultiples of the sampling frequency F_(s) by converting the signalcomponent to a direct current (DC) charge, and converting the aliases ofnoise to a sinusoidal charge which is removed during the integrationstate. The second processing stage of voltage-to-converter circuit 306as shown in FIG. 9 prevents aliases of noise at half of the samplingfrequency F_(s) by subtracting the charges of successive samples inphases A and B, using a differentiator, and then converting the noise toa frequency which can be distinguished from the signal. The noise canthen be subtracted from the signal, thus preventing noise at half of thesampling frequency.

FIG. 11 is a flowchart illustrating a method for generating a signalproportional to a charge of a capacitor having reduced noise consistentwith some embodiments. The method illustrated in FIG. 11 may beperformed by any of the embodiments herein, and will be discussed inaccordance with some of the embodiments disclosed herein. First, areference current I_(Ref) is supplied to sense capacitor 302 by acurrent source in charge-to-voltage converter circuit 304 (step 1102).The reference current I_(Ref) generates a time-varying voltage V_(s) onsense capacitor 302 (step 1104). Over time, the time-varying voltageV_(s) builds up on sense capacitor 302 and, thus, the time-varyingvoltage V_(s) is periodically reset by charge-to-voltage convertercircuit 304 (step 1106). According to some embodiments, the time-varyingvoltage V_(s) build up on sense capacitor 302 may be reset by togglingswitch 406 which provides a path to ground with a reset pulse P_(rst),as shown in FIG. 4. In other embodiments, the time-varying voltage V_(s)build up on sense capacitor 302 may be reset by applying a secondcurrent source having an equal magnitude but opposite polarity −I_(Ref)to sense capacitor 302, as shown in FIG. 8.

The time-varying voltage V_(s) generated by supplying the referencecurrent I_(Ref) to sense capacitor 302 is sampled by voltage-to-chargeconverter circuit 306 (step 1108). The time-varying voltage V_(s) isaccumulated on a capacitor such as capacitor 504, 604 or 904, therebygenerating a charge proportional to the charge on sense capacitor 302(step 1110). The generated charge produces an integration voltageV_(int) that is accumulated an integrator circuit 308, where theintegration voltage V_(int) is applied across an integration capacitor310 and generates a charge that is proportional to the charge on sensecapacitor 302 (step 1112). The charge accumulated on integrationcapacitor is integrated over time, and then measured to provide areading of the charge stored on sense capacitor 302 (step 1114).

Embodiments as described herein may provide a two-stage circuit forreducing noise in a capacitive sensing device, and a method thereof.Consistent with some embodiments, the circuit and method describedherein may provide greater elimination of aliasing noise by avoidingaliasing altogether. The examples provided above are exemplary only andare not intended to be limiting. One skilled in the art may readilydevise other systems consistent with the disclosed embodiments which areintended to be within the scope of this disclosure. As such, theapplication is limited only by the following claims.

What is claimed is:
 1. A capacitive sensing circuit, comprising: a firstcapacitor; a charge-to-voltage converter circuit coupled to the firstcapacitor, the charge-to-voltage converter circuit including a firstcurrent source that provides a first current to the first capacitor tocharge the first capacitor and generate a time-varying voltage; avoltage-to-charge converter circuit coupled to the charge-to-voltageconverter circuit, the voltage-to-charge converter circuit sampling thetime-varying voltage and converting the time-varying voltage into asampled charge at a predetermined sampling frequency; and an integratorcircuit coupled to the voltage-to-charge circuit, the integrator circuitreceiving the sampled charge and integrating the sampled charge.
 2. Thecircuit according to claim 1, wherein a voltage build up on the firstcapacitor is periodically reset to zero.
 3. The circuit according toclaim 2, wherein the voltage build up is periodically reset to zero byproviding a path to ground toggled by a reset pulse having apredetermined frequency.
 4. The circuit according to claim 3, whereinthe voltage-to-charge converter circuit comprises: a first switchcoupled to the charge-to-voltage converter circuit; a second capacitorcoupled to the first switch; a second switch coupled between the secondcapacitor and ground; a third switch coupled between the secondcapacitor and ground; and a fourth switch coupled between the secondcapacitor and the integrator circuit, wherein: the first and thirdswitch open and the second and fourth switch close on the falling edgeof the reset pulse.
 5. The circuit according to claim 4, wherein thepredetermined frequency is equal to the sampling frequency.
 6. Thecircuit according to claim 3, wherein the voltage-to-charge convertercircuit comprises: a first switch coupled to the charge-to-voltagecircuit; a second capacitor coupled to the first switch; a second switchcoupled between the second capacitor and the integrator circuit; a thirdswitch coupled between the second capacitor and a first voltage source;a fourth switch coupled between the second capacitor and a secondvoltage source; a fifth switch coupled between the second capacitor andground; a sixth switch coupled between the charge-to-voltage convertercircuit and a third capacitor; and a seventh switch coupled between thethird capacitor and the integrator circuit, wherein: the sampled chargeis transmitted to the integrator circuit a single sampling periodfollowing a falling edge of the reset pulse.
 7. The circuit according toclaim 6, wherein the predetermined frequency is an integer multiple of asampling period of the sampled charge.
 8. The circuit according to claim2, wherein the voltage build up is periodically reset to zero using asecond current source, the second current source providing a secondcurrent having a magnitude that is equal to a magnitude of the firstcurrent but having a polarity that is opposite to a polarity of thefirst current.
 9. The circuit according to claim 8, wherein thecharge-to-voltage converter circuit comprises: a charge switch and adischarge switch coupled between the first capacitor and a buffer,wherein the charge switch, when closed, couples the first current sourceto the first capacitor to charge the first capacitor; and the dischargeswitch, when closed, couples the second current source to the firstcapacitor to discharge the sense capacitor.
 10. The circuit according toclaim 9, wherein the first capacitor is charged over a full sampleperiod, and the first capacitor is discharged over the subsequent fullsample period.
 11. The circuit according to claim 8, wherein thevoltage-to-charge circuit is configured to generate the sampled chargeto be proportional to an absolute value of the time-varying voltage withrespect to a reference voltage source.
 12. The circuit according toclaim 8, wherein the voltage-to-charge circuit comprises: a first switchcoupled between the charge-to-voltage circuit and a second capacitor; asecond switch coupled between the second capacitor and the integratorcircuit; a third switch coupled between a reference voltage source andthe second capacitor; a fourth switch coupled the reference voltagesource and the second capacitor; a fifth switch coupled between thecharge-to-voltage circuit and a third capacitor; and a sixth switchcoupled between the third capacitor and the integrator circuit.
 13. Thecircuit according to claim 12, wherein the voltage-to-charge convertercircuit samples the time-varying voltage in a sampling stage and sendsthe sampled charge to the integrator circuit in an integration stage,and further wherein: during the first sampling stage, the first switch,the fourth switch, and the fifth switch are closed, while the second,third, and sixth switches are open, coupling the time-varying voltage tothe second capacitor; and during the integration stage, the second,third, and sixth switches are closed, while the first, fourth, and fifthswitches are open, coupling the second capacitor storing the sampledcharge to the integrator circuit.
 14. The circuit of claim 12, whereinthe voltage-to-charge converter circuit includes at least two processingstages which operate in parallel, the first processing stage removesnoise at integer multiples of a sampling frequency of sampling thecharge, and the second processing stage removes noise at half of thefrequency of the sampling frequency.
 15. A method of generating a signalproportional to a charge of a capacitor, the generated signal havingreduced noise, comprising: generating a time-varying voltage across afirst capacitor by supplying a first current produced by a first currentsource to the capacitor, wherein a voltage build up on the firstcapacitor is periodically reset; sampling the time-varying voltage;generating a proportional charge that is proportional to a charge storedon the first capacitor based on the sampled time-varying voltage; andaccumulating the proportional charge on a second capacitor.
 16. Themethod of claim 15, wherein periodically resetting the voltage build upon the first capacitor comprises generating a reset pulse at a firstpredetermined frequency, the reset pulse toggling a switch that providesa path to ground.
 17. The method of claim 16, wherein generating aproportional charge comprises: sampling the time-varying voltage acrossa third capacitor at a second predetermined frequency; and providing apath from the third capacitor to the second capacitor in response to afalling edge of the reset pulse.
 18. The method of claim 15, whereinperiodically resetting the voltage build up on the first capacitorcomprises: periodically stopping the supply of the first current to thefirst capacitor; and supplying a second current from a second currentsource to the first capacitor, the second current having a magnitudethat is equal to a magnitude of the first current but having a polaritythat is opposite to a polarity of the first current.
 19. The method ofclaim 18, wherein generating the proportional charge comprises: samplingthe time-varying voltage across a third capacitor; periodically couplingthe third capacitor to a reference voltage source; and after couplingthe third capacitor to the reference voltage source, periodicallycoupling the third capacitor to the second capacitor.
 20. The method ofclaim 19, wherein the proportional charge is proportional to thetime-varying voltage and the reference voltage.